The need to perform both functional and timing design verification of an integrated circuit (IC) requires the use of a simulation test bench environment. The simulation test bench environment is a collection of components designed to emulate the specified operation of an integrated circuit. The collection of components may consist of, but is not limited to, behavioral bus functional models, behavioral device functional models, primitive cell models, hardware description language (HDL) functional code, memory models, and gate-level circuitry, in order to emulate an actual system environment.
Previously, old design verification methodologies used low-level programming techniques to create functional test vectors (input stimulus), required manual graphical visual verification of correct protocol and timing verification, and had limited real-time data integrity checking capability.
The simulation test bench environment of the present invention utilizes high-level task routines executed by bus functional devices models to generate input test vectors. The present invention further utilizes built-in protocol and timing verification of the device under test (DUT) by a dedicated bus device model, and performs real-time data integrity checking of actual to expected data for all input/output (I/O) data transaction cycles in order to perform functional and timing design verification of an integrated circuit.